1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to improvement in a semiconductor memory device such as a MOS (metal oxide semiconductor) dynamic type RAM (random access memory) provided with active pull-up circuits.
2. Description of the Prior Art
In general, a MOS dynamic type RAM comprises a plurality of pairs of bit lines and a sense amplifier provided for each pair of bit lines. Before reading out information from a memory cell, the potentials of a corresponding pair of bit lines are precharged to a supply potential V.sub.CC . When the memory cell for reading information is selected to cause small potential difference between the corresponding pair of bit lines, the potential of the lower level one of the bit line pair is lowered to a ground potential V.sub.SS by the sense amplifier. Thus, the sense amplifier is adapted to detect and amplify the small potential difference between the corresponding pair of bit lines thereby to read information from the memory cell. In practice, however, the higher level one of the bit line pair may be slightly lowered by discharge upon starting of the aforementioned sensing operation or current leakage after completion of the sensing operation. In such case, the level of rewriting in the memory cell is also lowered, and hence the conventional MOS dynamic type RAM may be provided with active pull-up circuits. Each active pull-up circuit is adapted to raise only the potential of the higher level bit line to the supply potential V.sub.CC. For example, U.S. Pat. No. 4,291,392 discloses a dynamic type memory device provided with such active pull-up circuits.
On the other hand the precharge level may be set at the intermediate level between the supply potential V.sub.CC and the ground potential V.sub.SS in order to reduce supply current when the bit line is charged or discharged, and also in this case, the potential of the higher level bit line must be raised to the supply potential level V.sub.CC by an active pull-up circuit.
FIG. 1 is a circuit diagram schematically showing an example of a conventional MOS dynamic type RAM provided with active pull-up circuit.
Description is now made on the structure of the circuit as shown in FIG. 1.
Referring to FIG. 1, a pair of bit lines BL and BL are provided to intersect with a word line WL and a dummy word line DWL respectively. A memory cell 10 is connected to the word line WL and the bit line BL, while a dummy cell 11 is connected to the dummy word line DWL and the bit line BL. In further detail, the memory cell 10 is formed by a MOS transistor 4 and a capacitor 8 of capacitance C.sub.M, and the MOS transistor 4 has a first electrode connected with the bit line BL, a second electrode connected with a cell plate electrode CP through the capacitor 8 and a gate electrode connected with the word line WL. The dummy cell 11 is formed by a MOS transistor 5 and a capacitor 9 of capacitance C.sub.D, and the MOS transistor 5 has a first electrode connected with the bit line BL, a second electrode connected with a cell plate electrode CP through the capacitor 9 and a gate electrode connected with the dummy word line DWL.
Further, a series circuit of MOS transistors 6 and 7 is connected between the pair of bit lines BL and BL. The MOS transistor 6 has a first electrode connected with the bit line BL and a second electrode connected with a first electrode of the MOS transistor 7. A second electrode of the MOS transistor 7 is connected with the bit line BL. A precharge potential V.sub.P (=1/2.multidot.V.sub.CC) is applied to the juncture between the second electrode of the MOS transistor 6 and the first electrode of the MOS transistor 7 for precharging the potentials of the pair of bit lines BL and BL. The MOS transistors 6 and 7 are on-off controlled by a precharge signal .PHI..sub.p applied to the respective gate electrodes thereof.
On the other hand, a sense amplifier 12 formed by MOS transistors 1 and 2 is connected between the pair of bit lines BL and BL. A first electrode of the MOS transistor 1 is connected with the bit line BL and a second electrode thereof is connected with a first electrode of the MOS transistor 2. A second electrode of the MOS transistor 2 is connected with the bit line BL. The gate electrode of the MOS transistor 1 is connected with the bit line BL, and the gate electrode of the MOS transistor 2 is connected with the bit line BL. The juncture between the second electrode of the MOS transistor 1 and the first electrode of the MOS transistor 2 is grounded through a MOS transistor 3. The MOS transistor 3 is on-off controlled by a sense amplifier activating signal S.sub.0 applied to its gate electrode. Namely, the operation of the sense amplifier 12 is controlled by the sense amplifier activating signal S.sub.0 to detect the potentials of the pair of bit lines BL and BL and lower the potential of the lower level bit line to a ground potential V.sub.SS.
Further, an active pull-up circuit 13 is connected between the pair of bit lines BL and BL. This active pull-up circuit 13 is controlled by an active pull-up signal AR, to pull up the potential of the higher level one of the pair of bit lines BL and BL to the supply potential V.sub.CC.
For the sake of convenience, FIG. 1 shows only one pair of bit lines, one word line, one dummy word line, one memory cell, one dummy cell, a group of precharging MOS transistors and one active pull-up circuit. However, an actual MOS dynamic type RAM is provided with a plurality of pairs of bit lines intersecting with a plurality of word lines and a plurality of dummy word lines. A memory cell is connected between one of each pair of bit lines and each word line. Further, a dummy cell is connected to each dummy word line for each pair of bit lines. Such memory cells and dummy cells are arrayed in the form of a matrix to form a memory cell array. Further, a group of precharge MOS transistors, one active pull-up circuit and one sense amplifier are connected with each pair of bit lines.
FIG. 2 is a timing chart for illustrating the read/write operation of the conventional MOS dynamic type RAM as shown in FIG. 1.
With reference to FIG. 2, description is now made on the operation of the circuit as shown in FIG. 1. Referring to FIG. 2, symbol EXT.multidot.RAS represents an external row address strobe signal, symbols RAS and RAS represent internal row address strobe signals, symbol WL represents potential change of the word line WL, symbol DWL represents potential change of the dummy word line DWL, symbol BL represents potential change of the bit line BL and symbol BL represents potential change of the bit line BL. The internal RAS signal, the precharge signal .phi..sub.p, the sense amplifier activating signal S.sub.0 and the active pull-up signal AR are generated from a conventional circuit (not shown) in sequence after generation of the external RAS signal.
It is assumed here that data "1" is written in the memory cell 10 and data "0" is written in the dummy cell 11. As shown in FIG. 2, during when the external RAS signal is at an "H" level, i.e., when the MOS dynamic type RAM is in a non-active cycle, the precharge signal .phi..sub.p is at an "H"level, whereby the MOS transistors 6 and 7 are brought into ON states and the potentials of the pair of bit lines BL and BL are precharged to the precharge voltage V.sub.P =(1/2.multidot.V.sub.CC).
Then, the external RAS signal falls at a time t.sub.1 and the internal RAS signal rises and the internal RAS signal falls slightly after the same so that the MOS dynamic type RAM enters an active cycle. At the same time, the precharge signal .phi..sub.P falls to complete the operation for precharging the bit lines BL and BL.
Then, a row address signal (not shown) is latched to be supplied to a row decoder (not shown), which in turn decodes the row address signal. WL and DWL rise at a time t.sub.2, whereby the word line WL and the dummy word line DWL are selected. As a result, the memory cell data is read on the bit line BL from the memory cell 10 and the dummy cell data is read on the bit line BL from the dummy cell 11, to cause potential difference between the pair of bit lines BL and BL. In order to read/write the memory cell data at the full level, the respective potentials of the word line WL and the dummy word line DWL are raised up to V.sub.CC +V.sub.TH +.alpha., where V.sub.TH represents the threshold voltage of the MOS transistors 4 and 5.
Then, the sense amplifier activating signal S.sub.0 rises at a time t.sub.3, to start the sensing operation. Namely, the sense amplifier 12 detects the potentials of the pair of bit lines BL and BL, to lower the potential of the lower level bit line BL to the ground potential V.sub.SS. The potential of the higher level bit line BL is also slightly lowered at this time.
Then, the active pull-up signal AR rises at a time t.sub.4 to drive the active pull-up circuit 13, which in turn pulls up the potential of the higher level bit line BL to the supply potential V.sub.CC.
Then, the external RAS signal rises at a time t.sub.5, whereby the internal RAS signal falls and the internal RAS signal rises immediately in response thereto. Then the respective potentials of the word line WL and the dummy word line DWL and the sense amplifier activating signal S.sub.0 fall and further the active pull-up signal AR falls to complete the pull-up operation.
Then, the precharge signal .phi..sub.P rises to start precharging the potentials of the pair of bit lines BL and BL at the precharge voltage V.sub.P (=1/2.multidot.V.sub.CC), so that the MOS dynamic type RAM enters a non-active cycle.
As hereinabove described, the internal RAS signal defines non-active and active cycles of the MOS dynamic type RAM, so that the memory operation is performed in the active cycle. The period during when the external RAS signal is at an "L" level, i.e., the period corresponding to t.sub.5 -t.sub.1 is called as an active cycle time t.sub.AC.
The aforementioned active pull-up operation is generally started immediately upon starting of the sensing operation and ended immediately after rise of the external RAS signal, while the aforementioned active cycle time t.sub.AC must be sufficiently long in order to completely pull up the potential of the higher level bit line. Namely, when an active pull-up circuit is employed, the active cycle time t.sub.AC must be prolonged by the time required for raising the potential of the higher level bit line to the supply potential V.sub.CC in comparison with the case of employing no such active pull-up circuit, leading to a disadvantage in view of the operating speed.